RV-CONVERGE 2026: Latin American Workshop on RISC-V for the HPC and AI Convergence Era
Chairs Workshop
- Sandro Rigo, Associate Professor, University of Campinas, Brazil. (Lead Organizer)
- Arthur Lorenzon , Associate Professor, Federal University of Rio Grande do Sul.
Submission Format
- We will have peer-reviewed papers and invited contributions.
Description of the workshop
The traditional boundaries between scientific simulation and machine learning are dissolving in the era of exascale computing and pervasive AI. This “HPC and AI convergence” demands hardware that is not only powerful but also highly specialized and energy-efficient.
RISC-V has emerged as the pivotal architecture for this era. Unlike proprietary ISAs, RISC-V’s open and modular nature allows researchers and architects to implement domain-specific extensions (such as the RISC-V Vector extension – RVV) and custom AI accelerators directly into the silicon. For the Latin American community, RISC-V may offer a path toward technological sovereignty, enabling regional development of custom high-performance hardware without the constraints of restrictive licensing.
This workshop aims to bring together researchers, system designers, and practitioners to discuss the role of RISC-V in scaling AI workloads on HPC infrastructure, the maturity of the RISC-V software ecosystem, and the deployment of open-hardware initiatives in Latin America.